Role of artificial intelligence in semiconductor chip design

Artificial intelligence assists semiconductor chip design through automated physical layout analysis and optimized fabrication process modeling. Fine-tuned vision-language models and convolutional neural networks inspect complex circuit geometries to answer engineering queries. Additionally, Bayesian optimization algorithms partner with human engineers to refine multi-parameter fabrication recipes, significantly decreasing development costs.

Key facts

• Integrating artificial intelligence into computer-aided design frameworks shifts analog integrated circuit development from manual and algorithmic solutions to automated and intelligent paradigms ^[1].
• In analog circuit design, the GDSII file represents the industry-standard database encapsulating physical geometries and parasitic realities that define tape-out performance ^[2].
• The Inspector framework combines fine-tuned large language models and convolutional neural networks to evaluate GDSII files of analog circuits through a conversational interface ^[3].
• In layout analysis across four realistic tasks, the Inspector framework outperforms general-purpose massive vision-language models by up to 81% ^[4].
• THEIA provides a dataset of layout images paired with question-answer conversations and a benchmark using a fine-tuned vision-language model to analyze GDSII files ^[5], allowing designers to query physical layouts as intuitive entities ^[6].
• Across five realistic tasks, the fine-tuned vision-language model in THEIA surpasses general-purpose vision-language models by up to 73% ^[7].
• Developing semiconductor processes that fabricate transistors and memory cells presents a growing cost bottleneck ^[8], as these processes involve hundreds of steps conceived manually by highly trained engineers ^[9].
• A hybrid collaboration between humans and computers can reduce process development costs by half compared to relying on human experts alone ^[10].
• Bayesian optimization algorithms prove effective when semiconductor data is scarce ^[11].

Automated analysis of analog circuit layouts

The integration of artificial intelligence into computer-aided design frameworks marks a transition in analog integrated circuit engineering from manual and algorithmic solutions toward automated and intelligent paradigms ^[1]. In this domain, GDSII files represent the industry-standard database containing the most accurate source of circuit information, encapsulating the complex physical geometries and parasitic realities that govern tape-out performance ^[2].

To interpret GDSII layout data efficiently, researchers developed the Inspector framework ^[3]. Inspector combines fine-tuned large language models and convolutional neural networks to analyze GDSII files of analog circuits, establishing an interactive conversational interface between the tool and circuit designers ^[3]. In evaluations testing thousands of analog designs across four realistic tasks, Inspector demonstrated a lightweight solution that outperformed general-purpose massive vision-language models by up to 81% ^[4].

Multimodal layout analysis is further evaluated in the THEIA framework, which introduces a dataset containing thousands of layout images paired with question-answer conversations ^[5]. Along with this dataset, THEIA establishes a benchmark that employs a fine-tuned vision-language model to analyze analog circuit GDSII files directly ^[5]. This allows circuit designers to interact with and query physical layouts as intuitive, meaningful entities ^[6]. Across five realistic tasks covering thousands of analog designs, the fine-tuned vision-language model outperformed state-of-the-art general-purpose vision-language models by up to 73% ^[7]. This disparity highlights a fundamental performance gap between general-purpose multimodal reasoning and domain-specific layout understanding ^[12].

Semiconductor fabrication process optimization

Artificial intelligence also addresses critical bottlenecks in developing the semiconductor manufacturing processes needed to fabricate transistors and memory cells ^[8]. These fabrication sequences consist of complicated processes involving hundreds of steps that are conceived manually by highly trained engineers ^[9]. Process engineers face challenges associated with scaling 3D NAND, FinFETs, DRAM, and other devices ^[13]. When creating a memory hole in a 3D NAND device or etching another device feature, process engineers face well over a hundred trillion possible recipes for high-aspect-ratio etching ^[14].

Individual experiments can run more than a thousand dollars each due to the costs of materials, equipment, and analytical tools ^[15]. Because semiconductor experiments are expensive, engineers typically develop processes by testing on the order of just a hundred different parameter recipes, including plasma pressure and wafer temperature for manufacturing machines ^[16]. This limited data makes it difficult to create a predictive model with good accuracy down to the atomic scale ^[17].

To investigate cost reductions, researchers explored optimization algorithms based on Bayesian reasoning, where prior knowledge helps compute the chances that an uncertain choice might be correct ^[18]. Bayesian optimization algorithms can prove effective when there is scarce data, and scientists have previously investigated their use for other applications in the semiconductor industry ^[11].

Collaborative human-machine optimization workflows

Inspired by computer advances in chess and Go, researchers developed a game as a test bed for comparisons ^[19]. In experiments, participants used a lab simulator to etch a memory hole, which is a trench in a silicon dioxide film used to create a memory cell ^[20]. The participants consisted of three computer algorithms, three human senior engineers with doctorates who each had more than seven years of experience, and three human junior engineers with doctorates who each had less than one year of experience ^[21]. At the end of each round, players submitted a batch of one or more recipes, with each recipe costing US $1,000 for wafer and measurement costs and each batch costing $1,000 for tool operation ^[22].

The top performer was a human senior engineer who produced the requested memory holes at a total cost of $105,000, while only 13 out of 300 computer attempts—less than 5 percent—beat this human expert ^[23]. The senior engineers required roughly half the cost of the junior engineers for the same amount of progress ^[24]. Researchers suggested the computer algorithms failed because they lacked expert knowledge and wasted experiments navigating the vast number of possibilities ^[25].

In human engineering work, the process split into an initial rough-tuning stage with rapid improvement toward meeting the target, and a later fine-tuning stage with slow progress to meet all desired goals simultaneously ^[26]. Human engineers excel in the early stage of rough tuning by drawing on experience and intuition, whereas computer algorithms prove far more cost-efficient in the later stage of fine-tuning when striving to reach precise targets ^[27].

Under a hybrid approach where the best human player guided the algorithms, the target was reached with a cost of $52,000, which was just under half the cost of the human expert alone ^[28]. Such collaborations can reduce development costs by half compared to relying on human experts alone ^[10]. Adopting these workflows requires adjusting to human-machine differences, as human engineers often change just one or two parameters from experiment to experiment, while computers may alter more without explanation, making it difficult for humans to accept recipes they do not understand ^[29].